Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
A flash memory is a type of memory that can be erased and reprogrammed in blocks instead of one byte at a time. A typical flash memory comprises a memory array organized in columns and rows. Changes in threshold voltage of the memory cells, through programming of charge storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data value of each cell. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed, such as by charging the charge storage structure. The data in a cell of this type is determined by the presence or absence of the charge in the charge storage structure. The charge can be removed from the charge storage structure by an erase operation.
A NAND non-volatile memory array is typically organized such that a plurality of memory cells share a common access line (e.g., word line) and a plurality of series strings of memory cells are coupled to a common data line (e.g., bit line). Due in part to this structure, memory cells can suffer from program disturb during a programming operation. Program disturb is the change in the threshold voltages of memory cells that are not being programmed as a result of voltages being applied to common word and bit lines and/or coupling effects from adjacent memory cells being programmed.
For example, if a series string of memory cells is inhibited from being programmed, the adjacent series strings of memory cells, on either side of the inhibited series string, can affect the threshold voltages of the inhibited memory cells by floating gate-to-floating gate capacitive coupling between memory cells. This can have the effect of increasing the threshold voltages of the inhibited memory cells thus causing subsequent read errors.
One typical prior art way to reduce programming disturb is to generate a pair of programming pulses for each word line only during a fixed number of middle range programming pulses (e.g., a particular group of programming pulses of a series of programming pulses to program a memory cell). By alternating inhibition of the adjacent bit lines, one adjacent bit line of memory cells is programmed with the first of the pair of programming pulses and the other adjacent bit line of memory cells is programmed with the second of the pair of programming pulses. Thus, only one adjacent bit line of memory cells is programmed at any one time during the fixed number of pairs of programming pulses. A single programming pulse is used at other times during the series of programming pulses. However, using a fixed number of pairs of programming pulses can result in increased programming time as well as other drawbacks.
For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art to reduce the effects of program disturb in a memory device.